1. Field of the Invention
The present invention relates to a self-test circuit in an integrated circuit, and a data processing circuit.
2. Description of the Related Art
An optical scanning device is known that performs deflection scanning of optical beams, and an optical writing device is known that is related to electrophotographic image formation and that forms an image by performing image writing on the surface of a photoconductor using the optical beams subjected to deflection scanning by the optical scanning device. Such an optical writing device that is related to electrophotographic image formation is installed in, for example, a copying machine, a facsimile device, a printer, a printing machine, or a digital multifunction peripheral (MFP). In an optical writing device that is related to electrophotographic image formation, a technology is known in which optical sensors are arranged before and after the image area in a main scanning direction, and in which pulse-width modulation (PWM) data is used for the purpose of correcting the variation in the main scanning direction magnification, which is attributed to a rise in temperature, according to the duration of light detection by the optical sensors.
In a digital circuit including a large number of flip-flops (hereinafter, abbreviated as FFs), such as in a circuit in which the PWM technology is implemented; in the case of attempting a test for detecting defects in the FFs, the following issue arises. That is, if it is to be verified whether the target digital circuit for testing has been able to perform timing adjustment at the highest clock speed; then, at the time of performing a scan test during the operations in a scan operation mode of the digital circuit, it becomes necessary to perform the test at the highest clock speed of the chip.
However, in order to perform a test at the highest clock speed, in the clock line of the digital circuit performing high-speed operations, if a clock or a selector is additionally installed as a requirement for switching from the normal operation mode to the scan test, the following issue arises. That is, as a result of adding a clock or a selector required for switching to the scan test, even if an attempt is made to appropriately achieve a synchronous design of the digital circuit, timing adjustment of the entire circuit becomes a difficult task.
In that regard, for example, in the conventional technology disclosed in Japanese Unexamined Patent Application Publication No. 2004-325124, the following method is implemented in order to detect defects in the FFs. A frequency counter, which is used to monitor the operating frequency of the target circuit for testing via an external terminal of the chip, is installed in a semiconductor test device; and the detection of defects is done by lowering the operating frequency. For example, Japanese Unexamined Patent Application Publication No. 2004-325124 discloses a technology in which the semiconductor circuit that is designed to have synchronization according to clock signals is made to read test data representing a bit string for circuit operation test, and defects in the FFs in the semiconductor circuit are detected.
More particularly, Japanese Unexamined Patent Application Publication No. 2004-325124 discloses an invention in which, while maintaining the current logical state of the FFs, the operation mode of the semiconductor circuit is switched from the normal operation mode to the scan mode; and then the logical state of the FFs that are made to read the test data is checked. In Japanese Unexamined Patent Application Publication No. 2004-325124, the logical state of “1” or “0” stored in each FF, which has read the test data, is compared with a known bit in the test data; and the FFs in which the stored logical state is different than the known bit are determined to be defective.
However, if the method disclosed in Japanese Unexamined Patent Application Publication No. 2004-325124 is implemented, in the synchronous design of the target digital circuit for testing, even if an attempt is made to verify whether timing adjustment was correctly performed during the operations at the highest clock speed, there is a disadvantage as follows. That is, at the time of performing a scan test during a scan operation mode of the digital circuit, it is not possible to perform a test at the highest clock speed of the chip in which the digital circuit is mounted, thereby making the test ambiguous.